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RF2908
11
Typical Applications
* Digital Cordless Telephones * Secure Communication Links * Wireless LANs * Inventory Tracking * Wireless Security * Battery Powered Applications
915MHZ SPREAD SPECTRUM RECEIVER WITH PLL FREQUENCY SYNTHESIZER
Product Description
The RF2908 is a monolithic integrated circuit specifically designed for direct-sequence spread-spectrum systems operating in the 902MHz to 928MHz ISM band. The part includes a direct conversion receiver, quadrature demodulator, dual IF amplifiers with gain control and RSSI, onchip programmable baseband filters, dual data comparators, and a serially programmable 86-channel PLL frequency synthesizer. Two cell or regulated three cell (3.6V maximum) battery applications are supported by the part. The part is also designed to operate in compliance with FCC Part 15.247. The device is provided in 48-lead plastic LQFP packaging.
.362 .346 .006 .002 .020 .362 .346 .280 .272 .011 .007 .057 .053
.280 .272 7MAX 0MIN
.031 .021
.007 MAX
Optimum Technology Matching(R) Applied
Package Style: LQFP-48
uSi Bi-CMOS
Si BJT
GaAs HBT SiGe HBT
GaAs MESFET Si CMOS
Features
* FCC Part 15.247 Compliant * Direct Conversion Receiver
11
TRANSCEIVERS
MOUT Q 1,2 LNA LNA IN 6
IN Q 47,48 IF Amp Q Data Amp 39 Q DATA
* On-Chip 86 Channel Frequency Synthesizer * On-Chip Selectable IF Bandwidths * 2.7V to 3.6V Operation
+45 -45
RSSI Gain Control
42 IF OUT Q 19 IF OUT I
PLL Freq. Synth. IF Amp 23 24 11,12 MOUT I Ref 13,14 IN I I Data Amp
21 I DATA
Ordering Information
RF2908 915MHz Spread Spectrum Receiver with PLL Frequency Synthesizer
Refer to the Detailed Functional Block Diagram for description of full functionality
Functional Block Diagram
RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA
Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com
Rev C1 010904
11-85
RF2908
Absolute Maximum Ratings Parameter
Supply Voltage Control Voltages Input RF Level Output Load VSWR Operating Ambient Temperature Storage Temperature
Ratings
-0.5 to +3.6 -0.5 to +3.6 +20 50:1 -40 to +85 -40 to +150
Unit
VDC VDC dBm C C Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s).
Parameter
Overall
Frequency Range Cascaded Voltage Gain Cascaded Noise Figure Cascaded Input IP3 RX Sensitivity LO Leakage RSSI DC Output Range RSSI Sensitivity RSSI Dynamic Range
Specification Min. Typ. Max.
902 to 928 100 6.0 -12 +5.5 -100 -65 0.35 to 3.1 30 65 902 to 928 22 6.0 50 -20 -12 +5.5 3 1 200 33
Unit
MHz dB dB dBm dBm dBm dBm V mV/dB dB MHz dB dB dBm dBm dB mA
Condition
T=25 C, VCC =3.6V, Freq=915MHz
8.0
High Gain Low Gain IF BW =960kHz, Freq=915MHz, S/N=8dB At LNA IN RLOAD =51k
60
LNA and Mixer
Operating Frequency Range Voltage Gain Noise Figure RF Input Impedance RF Input VSWR Input IP3
8.0 2:1
11
TRANSCEIVERS
Quadrature Phase Balance Quadrature Amplitude Balance Mixer Output Impedance DC Current Consumption
5
At maximum gain. ATTN=LOW At minimum gain. ATTN=HIGH With expected LO amplitude and harmonic content. Differential Operating at a 3.3V supply voltage.
150 26
250 39
11-86
Rev C1 010904
RF2908
Parameter
IF and Data Amplifiers
IF Frequency Range Voltage Gain Noise Figure Input IP3 Output DC Offset Gain Control Range Gain Control Voltage Range Gain Control Sensitivity VGA Output Voltage VGA DC Output Voltage Output P1dB RSSI Range RSSI Output Voltage Compliance Input Impedance Note 1 77 80 5 35 -65 +2 0 70 -0.08 500 1.7 1.64 60 0.5 to 2.4 2 2.5 9.6 83 MHz dB dB dB dBm dBm mV dB V dB/mV mVPP V VPP dB V k
Specification Min. Typ. Max.
Unit
Condition
At maximum gain setting At minimum gain setting At maximum gain setting At minimum gain setting
25 2.0
65 1.2
1 55 1.5
Driving a 5k load At maximum gain setting Maximum RSSI is 2.5V or VCC -0.3, whichever is less. Differential Note 1. The lower cutoff frequency is a function of: a) input DC blocking cap size; b) DC feedback capacitor; and, c) gain setting. But, recommended component values will yield a cutoff of <10kHz. Five pole Bessel internal LPF. Three pole external LPF. Selectable from 1, 2, 4, and 8MHz. Refer to "IF Bandwidth Response" chart. At 8MHz, increasing as bandwidth decreases.
Filters
Characteristics Bandwidth Passband Ripple Group Delay Ultimate Rejection 80 100 100 10 2 VCC -0.3V 0.3 5 Five pole Bessel 1, 2, 4, 8 1 100 MHz dB ns dB dB MHz ns V V
Data Amplifiers
Voltage Gain Bandwidth Rise and Fall Time Logic High Output Logic Low Output
11
Can sink/source 1mA and maintain these logic levels. Can sink/source 1mA and maintain these logic levels. TRANSCEIVERS
PLL, Synthesizer, VCO and LO
VCO Tuning Range VCO Sensitivity Charge Pump Current Reference Frequency Crystal Reference Crystal Rs Phase Noise LO Output Level Lock Time Step Size 20 800 to 1200 30 100 9.6 60 -66 -96 -10 1.5 300 40 20 80 MHz MHz/V A MHz dBc/Hz dBc/Hz dBm ms kHz Determined by external resistor. KPD =100A/2=0.0159ma/2 rad
10kHz offset. 100kHz offset. Into 100 differential load From sleep mode. 86 channels in the 902MHz to 928MHz ISM band.
Rev C1 010904
11-87
RF2908
Parameter
Power Down Control
Logical Controls "ON" Logical Controls "OFF" Control Input Impedance Turn On Time VCC -0.3V 0 >1 1 VCC +0.3V 0.3 V V M ms Voltage supplied to the input Voltage supplied to the input Reference Crystal=9.6MHz. Dependent on reference crystal. Higher frequencies reduce turn on/off times. Reference Crystal=9.6MHz. Dependent on reference crystal. Higher frequencies reduce turn on/off times.
Specification Min. Typ. Max.
Unit
Condition
Turn Off Time
1
ms s 3.6 62 V mA A mA
RX to TX and TX to RX Time
100 2.7 3.3 50 50 45
Power Supply
Voltage Current Consumption VCC =3.3V; RX ENABL=HIGH; PLL ENABL=HIGH VCC =3.3V; Sleep Mode VCC =3.3V; RX ENABL=LOW; PLL ENABL=HIGH
57
11
TRANSCEIVERS
11-88
Rev C1 010904
RF2908
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Function MOUT QMOUT Q+ MIX VCC MIX GND LNA GND LNA IN SW GND LNA VCC SW GND2 ATTN MOUT I+ MOUT IIN I+ IN IGND2 DCFB I VCC2 GND3 IF OUT I VCC3 I DATA RSSI I OSC B OSC E LE PLL CLK PLL DATA Description
The complementary quadrature phase signal output from the front-end mixer. See pin 2. The quadrature phase signal output from the front-end mixer. Supply voltage for the front-end quadrature mixers. Ground connection for the front-end quadrature mixers. Ground connection for the low noise amplifier (LNA). Input to the attenuator and LNA. Ground connection for the input attenuator. Supply voltage for the LNA. Ground connection for the input attenuator. Input attenuator control point. When connected "high", the attenuator adds 20dB of series attenuation. When connected "low", the attenuator adds 0dB of series attenuation. The in-phase signal output from the front-end mixer. The complementary in-phase signal output from the front-end mixer. See pin 12. Input for the in-phase IF channel. Complementary input for the in-phase IF channel. Ground for VCC2. DC feedback capacitor for in-phase channel. Power supply for VGA amplifier 3, differential to single-ended converter, and post filter. Ground for VCC3. Analog signal IF output for in-phase channel. Power supply for data amplifier. Logic-level data output for the in-phase channel. This is a digital output signal obtained from the output of a Schmitt trigger. Received signal strength indicator for the in-phase channel. Base connection point for external reference crystal. The reference crystal is connected between this pin and ground. Emitter connection point for external reference crystal. Feedback capacitors are connected between this pin and ground. Latches data entered into the serial port. Data is clocked into the latch on the rising edge of LE. See table and timing diagram. PLL shift register clock. The rising edges of this clocking signal load in the serial data present at the PLL DATA input pin into the internal latch. See table and timing diagram. Input data for loading the counters. Clocked, serial data at this port is presented to the shift register, then to the latch, and finally to the counter. Each clock transition sends a single bit to the on-board 7-bit shift register. The MSB is loaded first. See table and timing diagram. Ground connection for the PLL. Supply voltage for the PLL. Complementary local oscillator output. See pin 33. This port is used to supply DC voltage to the VCO as well as tune the center frequency of the VCO. This is the complementary port to pin 31. Refer to pin 31. Local oscillator output. Connection point for the loop filter.
Interface Schematic
11
TRANSCEIVERS
28 29 30 31 32 33 34
PLL GND PLLD VCC LO OUT B RESNTR+ RESNTRLO OUT DO
Rev C1 010904
11-89
RF2908
Pin 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Function Description PLL ENABL This pin is used to power up or down the VCO and PLL. A logic high RX ENABL BW SEL2 BW SEL1 Q DATA RSSI Q VREF IF OUT Q VGC VCC1 DCFB Q GND1 IN QIN Q+ Interface Schematic
(PLL ENABL>2.0V) powers up the VCO and PLL circuitry. A logic low (PLL ENABL<1.0V) powers down the PLL and VCO. Enable pin for the receiver circuits. RX ENABL>2.0V powers up all receiver functions. RX ENABL<1.0V turns off all receiver functions except the PLL functions and the RF mixer. Bandwidth select logic input. Pin 37 and pin 38 provide a two bit control word for the setting of the IF bandwidth. See Table1. Bandwidth select logic input. Pin 37 and pin 38 provide a two bit control word for the setting of the IF bandwidth. See Table1. Logic-level data output for the quadrature channel. This is a digital output signal obtained from the output of a Schmitt trigger. Received signal strength indicator for the quadrature channel. Gain control reference voltage. Analog signal IF output for quadrature channel. Gain control voltage. Power supply for bias circuits and VGA amplifiers for both the in-phase and quadrature channels. DC feedback capacitor for quadrature channel. Ground for VCC1 for both the in-phase and quadrature channels. Minus input for quadrature channel Plus input for quadrature channel
Table 1: Bandwidth Selection Controls
BWSEL1 0 0 1 1
BWSEL2 0 1 0 1
11
TRANSCEIVERS
IF-3dB Frequency 1MHz 2MHz 4MHz 8MHz
11-90
Rev C1 010904
RF2908
Table 2: Channel Plan
Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
f, MHz
902.4 * 903 903.3 903.6 903.9 904.2 904.5 904.8 905.1 905.4 905.7 906 906.3 906.6 906.9 907.2 907.5 907.8 908.1 908.4 908.7
Data
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
f, MHz
909 909.3 909.6 909.9 910.2 910.5 910.8 911.1 911.4 911.7 912 912.3 912.6 912.9 913.2 913.5 913.8 914.1 914.4 914.7 915 915.3
Data
44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65
f, MHz
915.6 915.9 916.2 916.5 916.8 917.1 917.4 917.7 918 918.3 918.6 918.9 919.2 919.5 919.8 920.1 920.4 920.7 921 921.3 921.6 921.9
Data
66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85
f, MHz
922.2 922.5 922.8 923.1 923.4 923.7 924 924.3 924.6 924.9 925.2 925.5 925.8 926.1 926.4 926.7 927 927.3 927.6 927.9
*Data 1 is invalid. Timing Diagram
H
DATA
L
0 MSB
0
0
1
0
1
0 LSB
...
11
TRANSCEIVERS
H
CLK
L
tCWH
...
tCWL tCS tCH tES tEW
H
LE
L
...
time Example: Load Sequence for Channel #10 (905.4 MHz) Decimal 10 = 0 0 0 1 0 1 0 Binary MSB LSB t
Minimum Times: tCWH tCWL tEW tES tCS tCH = 143 ns = 143 ns = 74 ns = 143 ns = 36 ns = 36 ns
0
Rev C1 010904
11-91
RF2908
Differential Filter Design Information
Butterworth Response
RS
L
RL
C1 RS L
C2 RL
12 12 1 1 C1bw -- 10 C2bw -- 10 6 2 2 Lbw RL 10 C1 = ------------------------------------- ;C2 = ------------------------------------- ;L = ----------------------------------2 fc RL 2 fc RL 2 fc
C1bw = 4.5325 ;C2bw = 13.5691 ;Lbw = 0.1743 RS RS = 125 ;RL = 1000 ;------ = 0.125 RL
Differential LC Filter Component Values (Butterworth Response)
100000
11
TRANSCEIVERS
10000
Component Value
1000
100
C2 (pF)
C1 (pF)
10
L (H) 1 1.E+05
1.E+06 Frequency
1.E+07
11-92
Rev C1 010904
RF2908
Differential Filter Design Information (Cont.)
Bessel Response
RS
L
RL
C1 RS L
C2 RL
12 12 1 1 C1bw -- 10 C2bw -- 10 6 2 2 Lbw RL 10 C1 = ------------------------------------- ;C2 = ------------------------------------- ;L = ----------------------------------2 fc RL 2 fc RL 2 fc
C1bw = 2.6163 ;C2bw = 13.6373 ;Lbw = 0.1083 RS RS = 125 ;RL = 1000 ;------ = 0.125 RL
Differential LC Filter Component Values (Bessel Response)
100000
11
10000
Component Value
1000
100
C2 (pF)
C1 (pF) 10
L (H) 1 1.E+05 1.E+06 Frequency 1.E+07
Rev C1 010904
11-93
TRANSCEIVERS
RF2908
Pin Out
IF OUT Q BW SEL1 38 BW SEL2 37 36 RX ENABL 35 PLL ENABL 34 DO 33 LO OUT 32 RESNTR31 RESNTR+ 30 LO OUT B 29 PLLD VCC 28 PLL GND 27 PLL DATA 26 PLL CLK 25 LE 13 IN I+ 14 IN I15 GND2 16 DCFB I 17 VCC2 18 GND3 19 IF OUT I 20 VCC3 21 I DATA 22 RSSI I 23 OSC B 24 OSC E DCFB Q Q DATA 39 RSSI Q 40 GND1 VCC1 VREF 41 IN Q+ IN Q-
48 MOUT QMOUT Q+ MIX VCC MIX GND LNA GND LNA IN SW GND LNA VCC SW GND2 ATTN MOUT I+ MOUT I1 2 3 4 5 6 7 8 9 10 11 12
47
46
45
44
43
VGC
42
11
TRANSCEIVERS
11-94
Rev C1 010904
RF2908
Detailed Functional Block Diagram
MOUT QMOUT Q+ LNA VCC MIX VCC
10
8
LNA
4
1
2
48 47
44
VCC1
IN Q+
IN Q-
17
VCC2
ATTN
20 39 Q DATA 42 IF OUT Q 45 DCFB Q
LNA IN 6
0-25 dB 0-20 dB -12-+12 17dB 6 dB
SW GND1 7 SW GND2 9 LNA GND 5 PLL ON 35 RX ENABL 36 BW SEL2 37 BW SEL1 38 MIX VCC 3 MOUT I+ 11 MOUT I- 12 IN I+ 13 IN I- 14 OSC B 23
-0.5/-20.5
+45 -45
VCC3
22 RSSI I 41 VREF 40 RSSI Q
Chip Control
43 VGC 21 I DATA 19 IF OUT I 18 GND3 16 DCFB I Phase Detector Charge Pump 15 GND2 46 GND1 34 DO 7-Bit Swallow Counter 0-85 7 7-Bit Latch 7 7-Bit Shift Register 26 PLL CLK 25 LE 27 PLL DATA
Ref. Osc. 5-bit Counter /32 300 kHz
300 kHz 7-Bit Counter /94 Prescaler 32/33 VCO
OSC E 24 902-928 MHz
30 31 RESNTR+ LO OUT B
32 33 RESNTRLO OUT
28 PLLD GND
29 PLLD VCC
11
TRANSCEIVERS
Rev C1 010904
11-95
RF2908
Application Schematic 915MHz
+3.3V REG +3.3V REG Refer to Filter Design Information for Component Values L C 47pF L 0.1F C 0.1F 10 10 10 +3.3V REG +3.3V REG +3.3V REG
10 10 0.01F 0.01F 47pF
0.1F 10 8 3 1 2 47 48 44
47pF 17
0.1F
47pF 20
0.1F
47pF
6.8nH 6
LNA
39 42 0.27F 45
+45 -45
0-25 dB
0-20 dB
-12-12dB
17dB
6 dB
7 9 5 35 36 Refer to Filter Design Information for Component Values L 0.1F C L C
0.1F
-0.5/-20.5
56pF 1F 56pF
22 41 40
37 38 4 11 12 13 14
Chip Control
43 21 19 18 16 Phase Detector Charge Pump 15 46 34 7-Bit Swallow Counter 0-85 7 7-Bit Latch 7 7-Bit Shift Register 26 25 27 0.27F
Ref. Osc. 23 100pF 24 100pF 902-928 MHz VCO 5-bit Counter /32 300 kHz
300 kHz 7-Bit Counter /94 Prescaler 32/33
30
31
32
33
28
29 0.1F
11
6.8nH
6.8nH 47pF 2k 10 0.1F 4.7F 47pF +3.3V REG 220pF 2.2nF Loop Filter
TRANSCEIVERS
22k
11-96
Rev C1 010904
RF2908
Evaluation Board Schematic
(Download Bill of Materials from www.rfmd.com.)
GC IF VCC C46 1 F DCFBQ L8 10 H C26 470 pF C25 1 nF L9 10 H C24 100 nF 48 IN Q+ 1 C23 100 nF C22 220 nF C21 47 nF J8 IF OUT Q VREF C44 68 pF Q RSSI J7 Q DATA BW SEL1 BW SEL2 RX ENABL PLL ENABL 47 IN Q46 GND1 45 DCFB Q 44 VCC1 43 VGC 42 IF OUT Q 41 VREF 40 RSSI Q 39 Q DATA 38 BW SEL1 BW SEL2 37 RX 36 ENBL C14 220 pF R4 33 k C12 Open C11 47 pF L3 5.6 nH L2 5.6nH R7 0 C13 Open 50 strip J6 LO OUT C15 4.7 nF
J9 Q MIX OUT
50 strip
C42 10 pF
T2 5:1
C41 10 nF
MOUT QC40 10 nF R6 10 C33 10 nF C34 22 pF 2 MOUT Q+ 3 MIX VCC 4 MIX GND 5 LNA GND 6 LNA IN 7 SW GND
PLL ENABL 35 DO 34 LO OUT 33 RESNTR- 32 RESNTR+ 31 LO OUT B 30 PLLD VCC 29 PLL GND 28
VCC
J1 RF IN
50 strip
L5 8.2 nH
PLL VCC C9 10 nF C10 22 pF R3 0 C5 47 pF C6 Open R2 1 k
50 strip C7 Open
VCC R5 10 C35 10 nF C36 22 pF
8 LNA VCC 9 SW GND2 10 ATTN 11 MOUT I+ MOUT IGND2 IN I+ C39 10 pF T1 5:1 IN I12 C38 10 nF L6 10 H C16 470 pF L7 10 H C18 100 nF IF VCC I DCFB 2908400C20 220 nF J3 IF OUT
J5 LO OUTB
PLL VCC ATTN C37 10 nF 50 strip PLL DATA 27 PLL CLK 26 IF OUT I DCFB I I DATA OSC B OSC E RSSI I GND3 VCC2 VCC3 LE 25 C1 33 pF C2 68 pF X1 9.6 MHz I RSSI C43 68 pF IF VCC R11 27 k R10 12 k R9 27 k PLL DATA R8 12 k C3 10 nF C4 22 pF R2 1 k C45 1 F
J2 I MIX OUT
C19 13 100 nF
14
15
16
17
18
19
20
21
22
23
24
PLL CLK R13 27 k R12 12 k
LE
R7 0
11
TRANSCEIVERS
J4 I DATA
P2 P2-1 C27 100 pF C28 10 nF C29 100 pF C30 10 nF C31 100 pF C32 10 nF P2-3 1 2 3 IF VCC GND GC P3-3 P3-1
P3 1 2 3 Q RSSI GND I RSSI NC P4-1
P4 1 2 3 DCFBI GND
P5 AMP D-Sub NC P5-2 P5-3 NC 1 2 3 4 5 6 7 8 9 PLL CLK GND LE PLL DATA
P1 P1-1 1 2 P1-3 3 DCFBQ GND VREF P6-3 P6-1
P6 1 2 3 PLL VCC GND PLL ON P7-3 P7-1
P7 1 2 3 ATTN GND RX ENABL P8-3 P8-1
P8 1 2 3 BW SEL1 GND BW SEL2
NC NC NC P5-8
Rev C1 010904
11-97
RF2908
Evaluation Board Layout Board Size 3.050" x 3.050"
Board Thickness 0.032", Board Material FR-4, Multi-Layer Assembly
11
TRANSCEIVERS
11-98
Rev C1 010904
RF2908
Top
Mid 1
11
TRANSCEIVERS
Rev C1 010904
11-99
RF2908
Mid 2
Back
11
TRANSCEIVERS
11-100
Rev C1 010904
RF2908
RF2908 IF Bandwidth Response
65.0 55.0 45.0 35.0 25.0 15.0 5.0 -5.0 -15.0 -25.0 -35.0 0.1 1.0 10.0 100.0
Gain (dB)
BW_SEL (0-0) BW_SEL (0-1) BW_SEL (1-0) BW_SEL (1-1)
IF Frequency (MHz)
11
TRANSCEIVERS
Rev C1 010904
11-101
RF2908
IIP3 versus Voltage Gain
10.0 -40C 0.0 -10.0 -20.0 +25C +100C 30.0 35.0 40.0 -40C +25C +100C
Noise Figure versus Voltage Gain (Non-Matched Input Z)
Noise Figure (dB)
25.0
IP3 (dB)
-30.0 -40.0 -50.0 -60.0 -70.0 -80.0 0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0 90.0
20.0
15.0
10.0
5.0
0.0 0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0 90.0
Voltage Gain (dB)
Voltage Gain (dB)
Voltage Gain versus Gain Control Voltage
90.0 -40C 80.0 70.0 60.0 50.0 40.0 30.0 20.0 10.0 0.0 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 +25C +100C
11
TRANSCEIVERS
Voltage Gain (dB)
Gain Control Voltage (V)
11-102
Rev C1 010904

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